Dodatne informacije

• Lični podaci

• Obrazovanje

• Fakultet: Elektronski fakultet
• Odsek / Grupa / Smer: Telekomunikacije
• Godina diplomiranja: 1977

• Spisak publikacija

• Radovi u časopisima sa IMPACT faktorom:

  N. Janković,  D. Pantić, S. Batcup, P. Igić,  LD MagFET - A Lateral Double-diffused Magnetic sensitive MOSFET with integrated n-type Hall plate,  Applied Physics Letters, Vol. 100, No. 26, pp. 263507 (1-4) , 2012.

  
  

  N. Jankovic,  Numerical simulations of N-type CdSe poly-TFT electrical characteristics with trap density models of Atlas/Silvaco, Microelectronics Reliability, 2012,  (Article in press, Available online 17 April 2012) 

  
  

  N. Jankovic, V.Brajovic, V_th compensated AMOLED pixel employing dual-gate TFT driver, IET Electronics Letters, Vol. 47, No. 7, pp.456–457, 2011.

  
  

  N. Janković, Compact model of the IGBTs with localized lifetime control dedicated to power circuit simulation,  Solid-State Electronics,  Vol.54 , pp. 268-274 , 2010.

• Radovi na naučnim skupovima međunarodnog značaja:

  N. Janković, S. Aleksić and D. Pantić, Simulation and Modeling of Integrated Hall Sensor Devices, Proc. Small Systems Simulation Symposium (SSSS 2012), Niš, Serbia, Feb.12-14, 2012, pp.85-92 (invited paper)

  
  

   

  
  

  V. Nikolić, N. Janković, A Simulation Study of Experimental GaInP/InGaAs/Ge Triple-Јunction Solar Cell, Proc. Small Systems Simulation Symposium (SSSS 2012), Niš, Serbia, 2012, pp. 14-19 .

  
  

  N. Jankovic, P. M. Holland, A. D. Johnson, S. Batcup, P. Igic, Optimizing the Efficiency of the InGaP/Ge Bottom Cell by Numerical Simulations, Next generation materials for concentrated solar energy conversion CPV and CSP, E-MRS 2011 Spring Meeting IUMRS ICAM 2011 & E-MRS / MRS Bilateral Conference on Energy , Nice, France,  May 9-13, 2011.

  
  

  T. Pesic-Brdjanin, N. Janković, D. Pantić, SPICE MAGFET model and its application for simulation of magnetically controlled oscillator, Proc. 26th Int. Conference on Microelectronics (MIEL08), May 2008, pp. 503-506.

  
  

  M. Lodzinski, N. Jankovic, O.J. Guy, P.M. Holland and P. Igic, A Novel n-Si/n-SiC Hetero-Junction Power Diode, Proc. 10th International. Seminar on Power Semiconductors (ISPS'08), Prague August, 2008.

  
  

  P. Igic, N. Jankovic, New High Voltage Partial SOI Technology for Smart-Power Applications, Proc.  10th International. Seminar on Power Semiconductors (ISPS'08),  Prague August, 2008.  

  
  

  N. Jankovic and P. Igic, SPICE Modeling of PT IGBT thermal behaviour,  Proc. 10th International. Seminar on Power Semiconductors (ISPS'08), Prague, August, 2008. 

• Patenti:

  - N. Jankovic, V.Brajovic:„Method and circuit for compensating pixel drift in active matrix displays”, pending patent, application filed in USA (2011) No: 61468874.

  
  

  - N. Jankovic, E.Bushehri:“CMOS compatible vertical NPN bipolar junction transistors and methods of producing them” , No: 2459695 (B), UK, published:  21-03-2012

  
  

  - N.Jankovic: ”CMOS static memory cell with complementary lambda bipolar transistors “, Patent Journal Yugoslavia, No. 5/88